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Sr. PD Timing Lead · Cupertino, CA
The SoC group has an opening for a Sr. Timing engineer. The successful candidate will be familiar with all aspects of timing of large high-performance SoC designs in sub-micron technologies. The candidate should be proficient in STA and methodologies for timing closure, and have a good understanding of noise, cross-talk, and OCV effects, among others. The candidate should also be familiar with circuit modeling, including SPICE models and worst-case corner selection.
The successful candidate will have an MSEE or equivalent and at least 10 years hands on experience in STA. Superior verbal and communication skills are a requirement
Required Skills:
See Job Description
Desired Skills:
Non-Tech Skills:
Start Date: ASAP
Emp. Type: Full Time
# of Openings: 1
Location: Cupertino, CA -
Overtime Pay: None
Job Number: 3948612
Date Posted: 9/2/2009
Apple Computer
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